This invention relates to integrated circuits and more particularly to the design and manufacture of integrated circuits that are optimized with respect to specified criteria.
Very Large Scale Integration (VLSI) is made possible by our technological ability to create electronic circuits having hundreds of thousands of transistors in a single chip. Efficient design of such VLSI circuits cannot be had without some automatic means for designing the interconnection patterns and for designing the layout of the circuits, including the creation of the active elements within the circuits. Not unexpectedly therefore, a number of products are available in the art that assist in the design of VLSI circuits. An integral part of such design tools is a means for evaluating the efficacy of the design. This includes means for measuring power consumption, speed of operation, area of the active elements, etc.
Timing analysis is one such tool, and is an important one because it is an essential element of any transistor sizing algorithm. Of course, the timing analysis is important in its own right to the designer of the circuit. In a paper titled "Synchronous Path Analysis in MOS Circuit Simulator," IEEE Proc. 19th Design Automation Conf., (1982), pp. 629-635, V. Agrawal describes an algorithm for estimating the time delay through a digital circuit. It is not the first such algorithm but it is an important one because it is able to discern the presence of latches (memory) in the circuit being investigated and is able to estimate the time delay from any input to any output of the combinatorial portion of the circuit. Two other timing analyzers are the Timing Verifier (TV) program by N. Jouppi, "Timing Analysis for NMOS VLSI," IEEE Proc. 20th Design Automation Conf., (June 1983), pp. 411-418, and the CRYSTAL program by J. Ousterhout, "Switch-Level Delay Models for Digital MOS VLSI," IEEE Proc. 21st Design Automation Conf., (June 1984) pp. 542-548. The CRYSTAL program is available commercially from the Regents of the University of California.
The CRYSTAL and TV programs differ from the Agrawal algorithm in that they use a more detailed timing estimation method, which takes into account differing gate delays for a single gate depending upon which input the signal arrives on. The drawback of both the TV and CRYSTAL programs is that they do not handle the presence of feedback in the integrated circuits, and that excludes almost all of the digital integrated circuits that are designed and built today.
Another important aspect of integrated circuit design is the transistor sizing approach that is employed. There are, of course, many deterministic sizing approaches. One simple approach, for example, is to create all transistors in one size that satisfies the circuit's overall speed requirement. In another, more sophisticated, approach the transistor size is related to how close the transistor is to the power (battery or ground) rail. There are also a number of algorithms that size the transistors within integrated circuits based on the specific circuit design. One of the earliest was the work of Ruehli, et al., described in "Analytical Power/Timing Optimization Technique for Digital System," IEEE Proc. 14th Design Automation Conf., (June 1977), pp. 142-146. They devised their own timing analyzer and with the aid of that analyzer they developed an algorithm for sizing transistors. Their timing analyzer, however, does not have the ability to recognize and deal with the presence of memory in the circuit. It also does not take into account the additional delay accruing from increasing the size of a transistor gate and thereby increasing the capacitance that needs to be driven. An algorithm that does take into account the increased gate capacitance was proposed by M. Matson in "Optimization of Digital MOS VLSI Circuits," Proc. Chapel Hill Conf. on VLSI, (University of North Carolina, May 1985), pp. 109-126. Matson's algorithm also uses a more accurate delay model for the active elements, which takes into account the slope of the input waveform.
The biggest drawback of Matson's algorithm and of all other known sizing algorithms is that they do not have the capability to automatically recognize and deal with feedback generally, and with memory elements in particular. This is a critical failing because essentially all digital integrated circuits are sequential circuits, and sequential circuits contain memory. Another drawback of these algorithms is their use of unnecessarily accurate optimization algorithms, which result in unacceptably show analysis of large integrated circuit designs.
It is an object of our invention to overcome the limitations of the above prior are methods with a system for designing integrated circuits that optimizes the circuits with respect to speed of operation, the area occupied by the active elements, or a combination of both.
It is another object of our invention to realize a system that assists in the design of integrated circuits by judicious sorting of subnetworks to optimize the circuits' operational speed, size of the active area, or both.